Risorse bibliografiche
Risorsa bibliografica obbligatoria
Risorsa bibliografica facoltativa
Scheda Riassuntiva
Anno Accademico 2019/2020
Scuola Scuola di Ingegneria Industriale e dell'Informazione
Docente Geraci Angelo
Cfu 5.00 Tipo insegnamento Monodisciplinare
Didattica innovativa L'insegnamento prevede  3.0  CFU erogati con Didattica Innovativa come segue:
  • Blended Learning & Flipped Classroom

Corso di Studi Codice Piano di Studio preventivamente approvato Da (compreso) A (escluso) Insegnamento

Obiettivi dell'insegnamento

The course aims to provide advanced operational skills in the implementation of processing digital architectures specifically in spatial configurable devices (i.e. FPGAs).

By combining and extending the competences of digital electronics toward designs that involve high-speed and high-efficiency digital signals and processing architectures, students are prepared for the challenges awaiting them in the realization of the most modern digital electronic systems.

Risultati di apprendimento attesi

Dublin Descriptor 1: Knowledge and understanding
Expected learning outcomes:

· Understand the principles of Configurable Computing

· Understand implementation issues in spatial computing devices (FPGAs)

· Know how to implement a digital design in a FPGA device

· Know basics of DSP algorithms designed for implementation in FPGA devices

· Understand pipeline and parallel processing

· Know pipeline and parallel implementation techniques of basic processing structures (FIR and IIR filters)

· Understand timing issues in a FPGA device


Dublin Descriptor 2: Applying knowledge and understanding
Expected learning outcomes:

·    Detail a set of requirements and design a corresponding digital processing architecture

·    Analyze specific architectural choices

·    Apply design principles to assess the availability of a processing architecture

·    Design, implementation and test of digital processing architectures in FPGA devices fulfilling a set of specifications


Dublin Descriptor 3: Making judgements
Expected learning outcomes:

· Identify the processing techniques and structures best suited to specific applications

· Evaluate the correctness of the architectures designed, identifying and defining the needed verification and validation activities

· Compare different possible implementations from performance and size point of view, identifying risks and potential mitigation actions


Dublin Descriptor 4: Communication
Expected learning outcomes:

· Write a requirement specification document

· Write a design specification document

· Present the work done also in front of colleagues


Dublin Descriptor 5: Lifelong learning skills
Expected learning outcomes:

· Learn how to develop a realistic project in a FPGA device

· Be able to learn new techniques and methods of digital signal processing

· Be able to contextualize learned knowledge and skills of digital signal processing in real application problems






Argomenti trattati

The course is based on the use of a personal laptop computer and of an Evaluation Board ("Basys 3 Artix-7 FPGA Trainer Board") whose supplying by the student is mandatory. Students enrolled in the course will be given precise indications for supplying the Evaluation Board.


Configurable Computing

  • Spatial vs. Temporal Computing
    -- FPGA Device
    -- Microprocessor Device
  • Implementation Issues
  • VHDL
  • Xilinx Vivado Design Suite


Introduction to Digital Signal Processing Algorithms

  • Typical DSP Agorithms
    -- Vision in Time and Frequency
    -- Convolution
    -- Correlation
    -- Digital Filters. FIR and IIR Filters
    -- Adaptive Filters
    -- Decimation and Oversampling
  • Representation of DSP Algorithms
    -- Block Diagrams
    -- Graph


Pipeline and Parallel Processing

  • Pipeline and Parallel Processing Overview
  • Filter Design in Matlab Environment
  • FIR Filters
    -- Pipelining
    -- Parallel Processing
    -- Combined Pipelining and Parallel Processing
  • IIR Filters
    -- Pipelining in 1st-Order and Higher-Order
    -- Parallel Processing
    -- Combined Pipelining and Parallel Processing
  • Pipelining and Parallel Processing for Low Power


Timing Issues in FPGA

  • Architecture Timing
    -- Clock Distribution
    -- Local Clocking
    -- Levels of Criticality
    -- Analysis
  • Clock Domain Crossing
    -- Sampling of Synchronous and Asynchronous Signals
    -- Interfacing different Clock Domains
    -- Hazards
  • Retiming Concept



  • Classroom Assignments
  • Homeworks



All contents of the course Sistemi Elettronici Digitali (code 085996) are mandatory.

Contents of the course Microcontrollori (code 099276) are recommended as well.

Modalità di valutazione

During the course there are 4 Labs in which a VHDL design to be developed and implemented in the FPGA on the Evaluation Board is proposed. Students can choose to attend to the Lab individually or independently organized in groups of up to three people. At the end of each Lab, a homework is proposed which the students, individually or independently organized in groups of up to three people, have to carry out within the next Lab (about 2 weeks later) and which will be evaluated with a score up to a maximum of 2.5 points, assigned equally to each member of the group. In the Labs students are provided with the necessary additional devices, such as joystick and audio modules to be connected to their Evaluation Board.
The written exam, with a maximum score of 15 points, consists of developing and implementing a VHDL design in the FPGA on the Evaluation Board. During the exam the student uses exclusively his own laptop, without Internet connection, and his own Evaluation Board. After the written exam the student can choose whether to keep valid the sum of the marks of the homeworks (maximum 10 points) and take a short oral exam with maximum score of 5 points or to take a complete oral exam with a maximum score of 15 points, disposing the scores of the homeworks.

Type of assessment: Written tests
Description of expected results according to Dublin descriptors (in brackets):

· Quantitative solution of problems (1,2)

· Exercises focusing on design issues (1,2,3,4,5)

· Questions on course topics with open answer (1,4,5)


Type of assessment: Oral exam
Description of expected results accordin to Dublin descriptors (in brackets):

· Assessment of the designs developed as part of laboratory activity, either homeworks and classroom works (2,3,4,5)


Risorsa bibliografica facoltativaVolnei A. Pedroni, Circuit Design and Simulation With VHDL, Editore: The MIT Press, Anno edizione: 2010, ISBN: 0262014335

Second Edition

Risorsa bibliografica facoltativaPeter J. Ashenden, The Designer's Guide to VHDL, Editore: Morgan Kaufmann, Anno edizione: 2006, ISBN: 0120887851

Third Edition

Risorsa bibliografica facoltativaDavid Harris, Sarah Harris, Digital Design and Computer Architecture, Editore: Morgan Kaufmann, Anno edizione: 2012, ISBN: 9789382291527

Second Edition

Forme didattiche
Tipo Forma Didattica Ore di attività svolte in aula
Ore di studio autonome
Laboratorio Informatico
Laboratorio Sperimentale
Laboratorio Di Progetto
Totale 50:00 75:00

Informazioni in lingua inglese a supporto dell'internazionalizzazione
Insegnamento erogato in lingua Inglese
Disponibilità di materiale didattico/slides in lingua inglese
Disponibilità di libri di testo/bibliografia in lingua inglese
Possibilità di sostenere l'esame in lingua inglese
Disponibilità di supporto didattico in lingua inglese
schedaincarico v. 1.6.2 / 1.6.2
Area Servizi ICT