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Scheda Riassuntiva
Anno Accademico 2019/2020
Scuola Scuola di Ingegneria Industriale e dell'Informazione
Insegnamento 052427 - ANALOG CIRCUIT DESIGN
Docente Lacaita Andrea Leonardo
Cfu 10.00 Tipo insegnamento Monodisciplinare
Didattica innovativa L'insegnamento prevede  1.0  CFU erogati con Didattica Innovativa come segue:
  • Blended Learning & Flipped Classroom

Corso di Studi Codice Piano di Studio preventivamente approvato Da (compreso) A (escluso) Insegnamento
Ing Ind - Inf (Mag.)(ord. 270) - MI (473) AUTOMATION AND CONTROL ENGINEERING - INGEGNERIA DELL'AUTOMAZIONE*AZZZZ095143 - ANALOG CIRCUIT DESIGN
Ing Ind - Inf (Mag.)(ord. 270) - MI (476) ELECTRONICS ENGINEERING - INGEGNERIA ELETTRONICA*AZZZZ052427 - ANALOG CIRCUIT DESIGN
095143 - ANALOG CIRCUIT DESIGN

Obiettivi dell'insegnamento

Aim of the course is to make students mastering the analysis and the design of CMOS amplifiers (OP-AMPs and OTAs) covering all the steps from topology choice, device sizing, compensation techniques, optimization of noise, power dissipation, bandwidth, large signal performance. As application cases, the amplifying blocks are adopted in designing analog filters.

Lectures are intended to deliver core concepts and methods, supported by notes and references to on-line material. Blended class sessions will present sample problems, guiding students to develop problem-solving strategies. Exercise classes will show students how to solve numerical problems thus strengthening their comprehension of the subjects. Labs are dedicated to design of CMOS amplifiers using CAD tools. The Lab activity provides realistic examples of the optimization procedures followed in real design practice. Design challenges are proposed during the course and active student participation is expected.


Risultati di apprendimento attesi

 

Expected learning outcomes

Dublin descriptor

On completion of this course, students will have a sound knowledge and understanding of design appraoches to:

·  OTAs and OP-AMPs;

·  continuous time active filters

 

1) knowledge and understanding

Specific examples and case studies will be provided to make students able to:

· analyse the requirements of CMOS amplifying stages

· define the circuit architectures suited to match the design targets

· size the components, accounting for noise and device variability

· implement frequency compensation techniques

· design continuous time analog filters

· refine the design supported by CAD tools adopted in real design practice.

2) applying knowledge and understanding

 


Argomenti trattati

Introductory concepts and background: The transistor as an amplifier, performance figures: maximum voltage gain, fT, power amplification and Johnson’s limit. MOSFET: quadratic I-V dependence, channel length modulation. Transconductance and maximum gain. Subthreshold operation. Dependence on bias point of transconductance and cut-off frequency. Stray capacitance. Multifinger MOSFET’s. Technology platforms.

OTA's and OP-AMP's: The differential stage with resististive loads. Performance of current mirrors. Effects of current mirror on differential and common mode gains. CMOS OTA’s. Two stages topology. Bias and systematic offset. Device Matching. Pelgrom’s formula. Input voltage offset. Cascoded mirrors. Impact on gain and CMRR. Frequency response. Pole splitting and GBWP. Slew Rate. GBWP/SR ratio. Alternative compensation strategies with buffers and nulling resistor. Single stage OTA’s. Telescopic/folded cascode topologies. Feed-forward compensation and impact on in-band doublet. Class AB OTA's. OP-AMPs and output stages.  

Complements on Noise: variance and power spectrum. Noise sources. Physical models of thermal noise and shot noise. Noise sources in FET's, input equivalent noise sources. 1/f noise and Tvidis formula. Input equivalent noise sources of OP-AMP’s.

Active filters: Introduction to active filters. First order cells. Canonical form for the pole pair. Q- factor of the pair. Filter sensitivity. Second-order cells. The Sallen-Key cell, loop gain, sizing options, impact on filter sensitivity. The Universal filter (KHN cell). Tow-Thomas cell. Options for filter synthesis: cascade of active cells, resonant ladder networks. Active inductors. Quality factor and noise. Implementation of active inductors with amplifiers and transconductors. Synthesis with integrators. Switched capacitor filters. SC-integrator. Output spectrum of a switched capacitor stage. Stray insensitive switches. Non-inverting integrator. Non-idealities of SC filters: finite gain, clock feed-through.


Prerequisiti

No formal pre-requisite exists. However, students are required to know the basics of linear circuit analysis, MOSFET operation, small signal operation and frequency response of elementary transistor topologies, principles of feedback theory and methods to assess and tailor stability margin of feedback circuits.


Modalità di valutazione

Assessment is based on a final exam consisting of a written exam followed by an oral. The written exam is a 3-hours, closed-book test devoted to the quantitative solution of two problems. Students who pass the written exam go through the oral exam, consisting of a discussion of two topics randomly picked from a list made available on BeeP. Those who have submitted solutions to the design challenges will have up to additional points. At the oral, the student is asked to discuss the selected topics, clearly stating the framework, deriving the quantitative results and, then, summarizing their main implications. The oral exam results in an adjustment (-2/30 to +2/30) of the written exam result, thus leading to the final grade.  

Type of assessment

Description

Dublin descriptor

Written exam

· Solution of quantitative problems (e.g. analysis of OTA scheme, deriving input referred-offset, noise, frequency response, large signal parameters etc.).

· Exercises focusing on design aspects (e.g. selection/design of OTA to match specs such as input/output voltage range, input-referred offset, noise, GBWP, slew rate, etc..).

1,2

 

 

1, 2

Oral exam

· Theoretical questions on topics covered by lectures.

· Discussion of design examples to verify the understanding.

1, 2

 


Bibliografia
Risorsa bibliografica obbligatoriaA. L. Lacaita, Lecture Notes made available on BeeP
Risorsa bibliografica facoltativaF. Maloberti, Analog Design for CMOS VLSI Systems, Editore: Springer Science and Business Media, Anno edizione: 2001, ISBN: 978-0-7923-7550-0

Forme didattiche
Tipo Forma Didattica Ore di attività svolte in aula
(hh:mm)
Ore di studio autonome
(hh:mm)
Lezione
60:00
90:00
Esercitazione
28:00
42:00
Laboratorio Informatico
12:00
18:00
Laboratorio Sperimentale
0:00
0:00
Laboratorio Di Progetto
0:00
0:00
Totale 100:00 150:00

Informazioni in lingua inglese a supporto dell'internazionalizzazione
Insegnamento erogato in lingua Inglese
Disponibilità di materiale didattico/slides in lingua inglese
Disponibilità di libri di testo/bibliografia in lingua inglese
Possibilità di sostenere l'esame in lingua inglese
Disponibilità di supporto didattico in lingua inglese
schedaincarico v. 1.6.1 / 1.6.1
Area Servizi ICT
28/01/2020