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Scheda Riassuntiva
Anno Accademico 2018/2019
Scuola Scuola di Ingegneria Industriale e dell'Informazione
Insegnamento 095942 - DIGITAL SYSTEMS DESIGN METHODOLOGIES
  • 095938 - DIGITAL SYSTEMS DESIGN METHODOLOGIES 1
Docente Ferrandi Fabrizio
Cfu 5.00 Tipo insegnamento Modulo Di Corso Strutturato

Corso di Studi Codice Piano di Studio preventivamente approvato Da (compreso) A (escluso) Insegnamento
Ing - Civ (Mag.)(ord. 270) - MI (495) GEOINFORMATICS ENGINEERING - INGEGNERIA GEOINFORMATICA*AZZZZ095941 - DIGITAL SYSTEMS DESIGN METHODOLOGIES 1
Ing Ind - Inf (Mag.)(ord. 270) - MI (476) ELECTRONICS ENGINEERING - INGEGNERIA ELETTRONICA*AZZZZ095942 - DIGITAL SYSTEMS DESIGN METHODOLOGIES
Ing Ind - Inf (Mag.)(ord. 270) - MI (481) COMPUTER SCIENCE AND ENGINEERING - INGEGNERIA INFORMATICA*AZZZZ095941 - DIGITAL SYSTEMS DESIGN METHODOLOGIES 1
095942 - DIGITAL SYSTEMS DESIGN METHODOLOGIES

Obiettivi dell'insegnamento

First emisemester of Digital Systems Design Methodologies. The whole course aims to present the design methodologies required to build complex digital systems.

The integration of tools and design methodologies will be addressed through a discussion of design for performance approaches, synthesis techniques starting from high-level specifications, IP modeling and complex system on chip integration, testing and verification of digital systems, system level modeling for complex digital systems and HW/SW co-design approaches. Two target technologies are addressed: application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs).


Risultati di apprendimento attesi

Knowledge and understanding

Students will learn how to:

- analyze and optimize the performance of a complex hardware design;

- optimize a logic description with respect to a given technology;

- analyze and optimize high-level specifications;

- synthesize complex operators.

Applying knowledge and understanding

Given specific problems, students will be able to:

- understand the complexity of hardware designs;

- understand possible optimizations for hardware designs;

- understand possible bottlenecks a given design may have.

Making judgments

Given a relatively complex design, students will be able to:

- understand if the obtained performance is in line with the expected performances (area, delay, power, etc.);

- understand if the proposed design fits the functional requirements;

- understand where previous approaches are relevant or not for a given problem.

Communication

Students will learn to:

- present their work discussing pros and cons of the proposed solution.

- present critically the existing state of the art showing where it could be improved or where it is inconsistent; 

Lifelong learning skills

Students will understand how a complex design, possibly interfaced with software, have to be analyzed, designed and assessed. They will play with real problems understanding where pitfall may come.


Argomenti trattati

Introduction

   The hardware design flow. Levels of Design Abstractions. The FSM-Datapath model.

Synthesis of digital systems

   Advanced logic synthesis techniques: Retiming and Resynthesis.

   Timing analysis and optimization, X-value simulation, sat-based analysis.

   High-level synthesis. Data flow and control flow graph construction. Datapath and controller architectures.

   The Scheduling and allocation problems: algorithms and constraints.

   Register allocation, Multi-cycling, Chaining, Pipelining.

   Synthesis of complex operator: array accesses and pointers arithmetic.

Application and platform modeling

   High-level languages (SystemC, timing diagrams, …).

   The co-simulation problem. A practical example of co-simulation applied to the high-level synthesis design flow.

   Example of platform modeling: modeling a Wishbone based platform.

   RTL IP modeling in VHDL/Verilog (memory units, pipelined units, etc) targeting FPGA technologies.

   Examples of design flows: ASIC vs FPGA design flow.

 

 


Prerequisiti

Some understanding of logic design methodologies, usually covered by the course “Reti Logiche”, is required.


Modalità di valutazione

The course corresponds to the first emisemester of Digital Systems Design Methodologies. The final exam is a written exam.

The following text provides a detailed overview of the elements that will be considered in the various assessment activities.

Written exam

Description of the existing solutions. Questions on the design of complex hardware systems. Numerical exercises assessing the quality of complex hardware/software systems. (Dublin descriptor 1,2,3,4,5)


Bibliografia
Risorsa bibliografica facoltativaG. De Micheli, Synthesis and Optimization of Digital Circuits, Editore: Mc Graw-Hill International Editions, Anno edizione: 1994
Risorsa bibliografica facoltativaM.Abramovici, M.A.Breuer, A.D.Friedman, Digital Systems Testing and Testable Design, Editore: Computer Science Press, Anno edizione: 1993
Risorsa bibliografica facoltativaG.D Hatchel, F. Somenzi, Logic synthesis and verification algorithms, Editore: Kluwer Academic Publishers, Anno edizione: 1996
Risorsa bibliografica facoltativaEdward A. Lee and Sanjit A. Seshia, Introduction to Embedded Systems, A Cyber-Physical Systems Approach, Anno edizione: 2011, ISBN: 978-0-557-70857-4 http://LeeSeshia.org
Risorsa bibliografica facoltativaAdditional material is available on the Beep platform of Politecnico di Milano https://beep.metid.polimi.it
Note:

access restricted to course participants


Forme didattiche
Tipo Forma Didattica Ore di attività svolte in aula
(hh:mm)
Ore di studio autonome
(hh:mm)
Lezione
30:00
45:00
Esercitazione
20:00
30:00
Laboratorio Informatico
0:00
0:00
Laboratorio Sperimentale
0:00
0:00
Laboratorio Di Progetto
0:00
0:00
Totale 50:00 75:00

Informazioni in lingua inglese a supporto dell'internazionalizzazione
Insegnamento erogato in lingua Inglese
Disponibilità di materiale didattico/slides in lingua inglese
Disponibilità di libri di testo/bibliografia in lingua inglese
Possibilità di sostenere l'esame in lingua inglese
Disponibilità di supporto didattico in lingua inglese
schedaincarico v. 1.6.5 / 1.6.5
Area Servizi ICT
11/08/2020