The course aims to present the design methodologies required to build complex digital systems.
The integration of tools and design methodologies will be addressed through a discussion of design for performance approaches, synthesis techniques starting from high-level specifications, IP modeling and complex system on chip integration, testing and verification of digital systems, system level modeling for complex digital systems and HW/SW co-design approaches. Two target technologies are addressed: application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs).
Detailed program first emisemester:
The hardware design flow. Levels of Design Abstractions. The FSM-Datapath model.
Synthesis of digital systems
Advanced logic synthesis techniques: Retiming and Resynthesis.
Timing analysis and optimization, X-value simulation, sat-based analysis.
High-level synthesis. Data flow and control flow graph construction. Datapath and controller architectures.
The Scheduling and allocation problems: algorithms and constraints.
Register allocation, Multi-cycling, Chaining, Pipelining.
Synthesis of complex operator: array accesses and pointers arithmetic.
Application and platform modeling
High-level languages (SystemC, timing diagrams, …).
The co-simulation problem. A practical example of co-simulation applied to the high-level synthesis design flow.
Example of platform modeling: modeling a Wishbone based platform.
RTL IP modeling in VHDL/Verilog (memory units, pipelined units, etc) targeting FPGA technologies.
Examples of design flows: ASIC vs FPGA design flow.
Detailed program second emisemester:
Testing of digital systems
Faults models and level of design abstractions. Testing at logic, functional and behavioral level of abstraction. Fault simulation algorithms. Automatic test pattern generation algorithms. Analysis and Design for Testability.
Verification of digital systems
Simulation based verification. Automatic test bench generation.
Equivalence checking. Tools for verification: Binary Decision Diagrams (BDD), Boolean Satisfiability applied to the verification problem.
Specifications and modeling at system level
Introduction to the system level modeling
Level of modeling abstractions
Models of computation and communication
Performance estimation for heterogeneous systems
Design solutions and models: Pareto analysis
Multi-objective design exploration algorithms.
Partitioning, allocation, mapping and scheduling.
Communication mapping and HW/SW interface synthesis.
Some understanding of logic design methodologies, usually covered by the course “Reti Logiche”, is required.