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Scheda Riassuntiva
Anno Accademico 2014/2015
Scuola Scuola di Ingegneria Industriale e dell'Informazione
Insegnamento 095143 - ANALOG CIRCUIT DESIGN
Docente Lacaita Andrea Leonardo
Cfu 10.00 Tipo insegnamento Monodisciplinare

Corso di Studi Codice Piano di Studio preventivamente approvato Da (compreso) A (escluso) Insegnamento
Ing Ind - Inf (Mag.)(ord. 270) - MI (419) INGEGNERIA ELETTRONICA* AZZZZ095143 - ANALOG CIRCUIT DESIGN
Ing Ind - Inf (Mag.)(ord. 270) - MI (436) INGEGNERIA DELL'AUTOMAZIONE* AZZZZ095143 - ANALOG CIRCUIT DESIGN
Ing Ind - Inf (Mag.)(ord. 270) - MI (473) AUTOMATION AND CONTROL ENGINEERING - INGEGNERIA DELL'AUTOMAZIONE* AZZZZ095143 - ANALOG CIRCUIT DESIGN
Ing Ind - Inf (Mag.)(ord. 270) - MI (476) ELECTRONICS ENGINEERING - INGEGNERIA ELETTRONICA* AZZZZ095143 - ANALOG CIRCUIT DESIGN

Programma dettagliato e risultati di apprendimento attesi

Introductory concepts and background: The transistor as an amplifier, performance figures: maximum voltage gain, fT, power amplification and Johnson’s limit. BJT’s: Gummel curves, generation and recombination, current density and bias point for optimum performance. Early effect and maximum voltage gain. MOSFET: quadratic I-V dependence, modulation of the channel length. Transconductance and maximum gain. Subthreshold operation and Ioff/Ion trade-off. Dependence on bias point of transconductance and cut-off frequency. Stray capacitance. Multifinger MOSFET’s. gm/C figure of merit. Technologies for integrated circuits: CMOS and BiCMOS platforms.

Operational Amplifiers: The differential stage with resististive loads. Performance of current mirrors. Effects of current mirror on differential and common mode gains. uA741: comments on the DC bias of the first stage. The second stage: bias and frequency response. Pole splitting and GBWP. Structure of the output stage: push-pull, crossover distortion, VBE multiplier.  Slew Rate. GBWP / SR ratio. Device Matching. Pelgrom’s formula. Input voltage offset. Input bias currents. Single stage OP-AMP’s. Frequency response. Feed-forward compensation. C-MOS OP-AMP’s. Two stages topology. Polarization of the basic configuration. Avoiding systematic offset. Signal feed-through and stability. Compensation with buffers and nulling resistor. Cascoded mirrors. Impact on gain and CMRR. CMOS bias networks. Single stage OTA. Telescopic/folded cascode topologies. Fully differential opologies, common-mode feedback network.

Complements on Noise: variance and power spectrum. Noise sources. Physical models of thermal noise and shot noise. Noise sources in BJT’s, input equivalent noise sources and their dependence on frequency. Noise sources in FET’s. 1/f noise and Tvidis formula. Input equivalent noise sources of OP-AMP’s.

Active filters: Introduction to active filters. First order cells. Canonical form for the pole pair. Q- factor of the pair. Filter sensitivity. Second-order cells. The Sallen-Key cell, loop gain, sizing options, impact on filter sensitivity. The Universal filter (KHN cell). Tow-Thomas cell. Options for filter synthesis: cascade of active cells, resonant ladder networks. Active inductors. Quality factor and noise. Implementation of active inductors with amplifiersa and transconductors. Synthesis with integrators. Switched capacitor filters. SC-integrator. Output spectrum of a switched capacitor stage. Stray insensitive switches. Non-inverting integrator. Non-idealities' of SC filters: finite gain, clock feed-through. Digital vs. Analog filters.

Labs are dedicated to design of CMOS amplifiers and active filters using CAD tools. The Lab activity provided realistic examples of the design process and and of the optimization procedures followed in professional practice. 

References

F. Maloberti : Analog Design for CMOS VLSI Systems – Kluwer Academic Publishers

A. S. Sedra, K. C. Smith: Microelectronic Circuits - Saunders College Publishing

A. Lacaita: Lezioni di Elettronica II - CUSL Milano (Italian)


Note Sulla Modalità di valutazione

The exam has a written test followed by an oral discussion.


Bibliografia

Mix Forme Didattiche
Tipo Forma Didattica Ore didattiche
lezione
60.0
esercitazione
32.0
laboratorio informatico
12.0
laboratorio sperimentale
0.0
progetto
0.0
laboratorio di progetto
0.0

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Area Servizi ICT
25/11/2020