• 095939 - DIGITAL SYSTEMS DESIGN METHODOLOGIES 2

Second emisemester of Digital Systems Design Methodologies. The whole course aims to present the design methodologies required to build complex digital systems.

The integration of tools and design methodologies will be addressed through a discussion of design for performance approaches, synthesis techniques starting from high-level specifications, IP modeling and complex system on chip integration, testing and verification of digital systems, system level modeling for complex digital systems and HW/SW co-design approaches. Two target technologies are addressed: application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs).

Knowledge and understanding

Students will learn how to:

- analyze and test a complex design;

- simulate and verify a complex design;

- model a complex embedded system;

- co-explore and co-design a complex hardware/software system.

Applying knowledge and understanding

Given specific problems, students will be able to:

- understand the complexity of hardware/software co-design;

- understand how to verify a complex system;

- understand possible bottlenecks a given design may have.

Making judgments

Given a relatively complex design, students will be able to:

- understand if the obtained performance is in line with the expected performances (area, delay, power, etc.);

- understand if the proposed design fits the functional requirements;

- understand where previous approaches are relevant or not for a given problem.

Communication

Students will learn to:

- present their work discussing pros and cons of the proposed solution.

- present critically the existing state of the art showing where it could be improved or where it is inconsistent; 

Lifelong learning skills

Students will understand how a complex design, possibly interfaced with software, have to be analyzed, designed and assessed. They will play with real problems understanding where pitfall may come.

Testing of digital systems

   Faults models and level of design abstractions. Testing at logic, functional and behavioral level of abstraction. Fault simulation algorithms. Automatic test pattern generation algorithms. Analysis and Design for Testability.

Verification of digital systems

   Simulation based verification. Automatic test bench generation.

   Equivalence checking. Tools for verification: Binary Decision Diagrams (BDD), Boolean Satisfiability applied to the verification problem.

   Introduction to hw-security approaches

Introduction to Low-Power design

Specifications and modeling at system level

   Introduction to the system level modeling

   Level of modeling abstractions

   Models of computation and communication

Co-exploration methodologies

   Performance estimation for heterogeneous systems

   Design solutions and models: Pareto analysis

   Multi-objective design exploration algorithms.

Co-synthesis methodologies

   Partitioning, allocation, mapping and scheduling.

   Communication mapping and HW/SW interface synthesis.

Some understanding of logic design methodologies, usually covered by the course “Reti Logiche”, is required.

The course corresponds to the second emisemester of Digital Systems Design Methodologies. The final exam is a written exam. It is possible to skip the written exam with a programming/modeling project.

The written exam is individual while the projects may be assigned up to two people.

The following text provides a detailed overview of the elements that will be considered in the various assessment activities.

Written exam

Description of the existing solutions. Questions on the design of complex hardware systems. Numerical exercises assessing the quality of complex hardware/software systems. (Dublin descriptor 1,2,3,4,5)

Oral presentation of the programming/modeling project (optional)

Assessment of the presentation of the programming/modeling project developed as part of course activities developed by students either individually or in groups. (Dublin descriptor 1,2,3,4,5)

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