This course provides the fundamentals of radio-frequency (RF) front-ends for wireless systems, with particular emphasis to the integration in CMOS and BiCMOS processes. Topics covered include: review of architectures of RF receivers/transmitters and digital modulations, design of building blocks (low-noise amplifiers, mixers, oscillators, frequency synthesisers). The primary goal of the course is to provide students with the basic skills and knowledge required to analyse and design practical RF circuits. Extensive laboratory experiences will be carried out using commercial tools, to show practical design flows at both system and circuit level.

Dublin Descriptor 1 (DD1): Knowledge and understanding

On completion of this course, students will be able to:

• comprehensively understand the principles and operation of modern wireless systems and the main sources of performance degradation;

• have a sound knowledge of techniques for frequency synthesis, and understanding of the operation of phase-locked loops;

• have a basic knowledge of reactive circuits used for impedance transformation and of practical realization of planar varactors, inductors and transformers;

• understand the basic working principles of oscillator circuits and the trade-off between phase noise and power dissipation;

• understand the impact of non-linearity on RF receiver performance and have a knowledge of the methods to measure non-linearity;

• have a knowledge and understanding of the circuit techniques to design low-noise amplifiers for RF applications;

• understand the working principles of mixer circuits;

• have a sound knowledge and understanding of the operation of basic RF receiver and transmitter architectures and their impact on building block design at circuit level.

Dublin Descriptor 2 (DD2): Applying knowledge and understanding

Specific examples and case studies will be provided to make students able to:

• evaluate the impact of circuit impairments (e.g. noise, mismatch, nonlinearity) on the performance of transmitter or a receiver for wireless application;

• model and simulate an RF transmitter at behavioral level, and evaluate the performance;

• handle jitter and phase noise calculations and their impact on SNR performance;

• design a frequency synthesizer based on a phase-locked loop for a given wireless application;

• model and simulate a phase-locked loop at behavioral level;

• design a passive network for impedance transformation;

• design a low-phase-noise oscillator circuit for a specific application;

• apply appropriate circuit techniques in the design of different types of low-noise amplifiers;

• choose among different types of mixer circuits and design;

• simulate RF circuits with commercially available software.

Lecture topics 

1. Basics of Communications Systems: AM and PM/FM modulations. Spectrum of a local oscillator, random-walk phase noise. SSCR, cycle jitter, absolute jitter. Digital communications: Nyquist signalling, constellation plane. BPSK/QPSK. Modulator and demodulator. Impact of I/Q mismatches and LO phase noise on EVM. Multiple access to channel. Heterodyne receiver architecture. Frequency synthesisers: specifications.
2. Phase-Locked Loop: behavioural description, nonlinear differential equation, perturbation analysis. PLL linear model. First- and second-order PLL.  Static phase error. Type-II PLLs. Phase noise. Capture range. Frequency synthesizers based on integer-N PLLs: behavior, phase noise, reference spurs. Charge-pump PLLs: type-II, tri-state phase detector, reference spur induced by non-ideality.
3. Passive Networks: Resonant circuits, voltage/current amplification, impedance transformation. L-match, Pi-match, Colpitts networks. Coupled inductors. Reactive components in silicon: spiral inductors, metal-metal capacitors, MOS and pn varactors.
4. Oscillator Circuits: feedback-system model, negative resistance model. Startup. Amplitude stabilisation. Frequency stability. Differential/single-ended CMOS/bipolar oscillators. Oscillator phase noise, noise-vs-power compromise.
5. Receivers and Amplifier Circuits: Third-order, second-order intercept point, two-tone test, cascaded stages. Maximum power transfer. Power gains. Scattering parameters. Noise figure: definition, calculation, cascaded stages. Noise matching, RX sensitivity and dynamic range. Low-noise amplifier (LNA) circuits: specifications (noise, linearity, matching, stability, gain, reverse isolation) and topologies (common-gate, inductive degeneration, shunt-feedback topology, noise cancelling technique).
6. Mixer Circuits: specifications (conversion gain, port-to-port feedthroughs), LO self mixing, noise, single- and double-balanced. Passive return-to-zero mixers, active mixers: conversion gain, linearity, noise.
7. Receiver/Transmitter Architectures: basic trade-offs in receivers, heterodyne receivers: image problem, half-IF problem, dual-IF receiver, direct-conversion receivers: LO leakage, I/Q mismatch, DC offsets, flicker noise. Image-reject architectures. IF receivers. Transmitter architectures.

Tutorial topics

1. Phase Noise: integrated phase noise, cycle jitter, reciprocal mixing
2. Phase-Locked Loop: Type-I PLLs, type-II PLLs. charge-pump PLLs
3. Passive Networks: Resonant circuits, coupled inductors, impedance transformation networks
4. Oscillator Circuits: differential/single-transistor CMOS/BJT topologies
5. LNA Circuits: basic topologies and feedback topologies, inductor-degeneration and noise cancelling
6. Mixer Circuits: passive and active topologies

Laboratory topics

1. QPSK Transmitter: modelling in Matlab of a raised-cosine QPSK TX, demodulation/signal analysis in Keysight VSA, study of impact of LO phase noise and I/Q mismatches.
2. Phase-Locked Loop: modelling and simulation in Matlab Simulink of type I, type II, charge-pump PLLs. Study of locking behavior.
3. Oscillator circuits: simulation of phase noise in Cadence SpectreRF of a differential CMOS LC oscillator at 1.5GHz.
4. LNA Circuits:  simulation of S-parameters, noise figure, IIP3 in Cadence SpectreRF of an inductive-degenerated amplifier at 1.5GHz.

A good understanding of linear circuit theory, the fundamentals of communication theory and control theory, as well as the basics of analog circuit design will be assumed. Those topics can be found in the following undergraduate courses at Politecnico di Milano: 082742 "Elettrotecnica", 086045 "Fondamenti di automatica", 085993 "Fondamenti di segnali e trasmissione", 085995 "Elettronica analogica".

Student Evaluation and Final Grades

The grade will be determined by the final examination which can be taken in one of the five examination dates along the academic year. The final examination consists of a 120-minutes closed-book written test and an oral examination. The written examination comprises two/three numerical problems with maximum score equal to 28/30 (cum laude), concerning topics 1., 2., 3., 4., 5., 6. of theory and tutorial. Alternatively, the written test can be split into a mid-term 90-minutes test (concerning topics 1., 2., 3. of theory and tutorial, and comprising one/two numerical problems) and a final 90-minutes test at the end of term (concerning topics 4., 5., 6. of theory and tutorial, and comprising one/two numerical problems).  Students who pass the written test may take an oral examination (max. score 2/30), consisting of a discussion on one topic picked at random from a given list of 40 questions. The final grade will be the sum of the grades of the written and the oral exams.

Assessment and Dublin Descriptor

Written examination:

• Solution of numerical problems (e.g. analysis of phase-locked loop systems, RF receivers, LNA, mixer or oscillator circuits, etc.): DD1, DD2

• Exercises focusing on design aspects (e.g. design of circuit/system for a specific wireless application or to meet given specifactions): DD1, DD2

Oral examination:

• Theoretical/practical questions drawn from any topic of the course: DD1, DD2