This course focuses on the design concepts and architectures underlying modern digital integrated circuits. The objective is to understand how to use individual devices to build combinational logic gates, sequential logic circuits, and complex architectures under constraints of reliability, dynamic performance, area, and power consumption.

Knowledge and understanding (Dublin Descriptor 1)

At the end of the course and after successfully passing the exam, the student:

•     knows how to analyse combinational and sequential digital circuits implemented in different logic families;

•     knows how to analyse the effect of interconnect parasitics on the performances of a digital circuit;

•     understand which implementation of a digital circuit is the most suited for a given constraint, i.e., area, power consumption, speed and reliability;

·      knows how to analyse simple digital modules, such as finite state-machines, counters (asynchronous and synchronous), memories (ROM, SRAM, DRAM) and arithmetic circuits (adders, multipliers, digital comparators, equality circuits).

Applying knowledge and understanding (Dublin Descriptor 2)

At the end of the course and after successfully passing the exam, the student:

•   is able to apply the acquired knowledge to assess the operation and performance of a digital integrated circuit;

•   is able to apply the acquired knowledge to design a combinational gate or a sequential circuit;

•   is able to discuss pros and cons and performance trade-offs between different implementations of the same circuit.

Introductory concepts and background: a historical perspective: from vacuum tube to transistor era, issues in digital integrated circuit design, quality metrics of a digital circuit (cost of an integrated circuit, functionality and reliability, static and dynamic performance, power and energy consumption).

The devices: the diode, the MOS(FET) transistor (static and dynamic behavior), velocity saturation, unified model, secondary effects, mismatch and process variations, technology scaling.

The wire: interconnect parameters (capacitance, resistance and inductance), electrical wire model (lumped and distributed RC models), Elmore theorem, transmission line, effects of scaling.

The CMOS inverter: the static CMOS Inverter, switching threshold, noise margins, propagation delay, dynamic power Consumption, static power consumption, power- and energy-delay product  technology scaling and its impact on the digital circuit metrics.

Combinational logic gates: static CMOS design, i.e., fully-complementary CMOS logic, pseudo-NMOS logic, differential cascode voltage switch logic (DCVSL), pass-transistor logic, dynamic logic (basic principles, speed and power dissipation of dynamic logic, cascading dynamic gates, domino gates).

Sequential logic circuits: latches and flip-flops as basic sequential element, timing metrics for sequential circuits, static latches and flip-flops (multiplexer-based latches, master-slave edge-triggered flip-flops), toggle flip-flops, dynamic latches and flip-flops, C2MOS latches, True Single-Phase Clocked (TCSP) flip-flops, pulseed flip-flops, pipelining as approach to optimizing sequential circuits, finite state-machines (FSMs). 

Arithmetic circuits: half-adder, full-adder, circuit implementation of single-bit adder, multi-bit adder (ripple carry, carry-skip, linear carry-select, root-square carry-select), multiplier (array and carry-save multiplier), digital comparators, 2’complement representatiojn of signed numbers, subtractors, digital comparators, equality circuits.

Semiconductor memories: memory classification, memory architectures and building blocks, read-only memories (ROM), flash memory, nonvolatile read-write memories (RAM), static RAM, dynamic RAM, memory peripheral circuitry (address decoders, sense amplifiers, voltage references, drivers/buffers). 

Students are required to know:

i) the basics of boolean algebra;

ii) the working principle of MOS transistors;

iii) basics of analog electronics.

The final examination consists of a written test followed by a Q&A session. The written test is made of three questions, each regarding one of the three macro-blocks of the course: combinational circuit deisgn/analysis, sequential cricuit design/analysis and digital module (finite state machine, arithmetic circuit or semiconductor memory) design/analysis. The oral examination is not compulsory. However, without taking oral examination the grade can be 24 at most.

The exam can be passed also by means of two mid-term tests, the first in the middle of the semester and the second at the end of the course, and a Q&A session.