• Blended Learning & Flipped Classroom

Aim of the course is to make students mastering the analysis and the design of CMOS amplifiers (OP-AMPs and OTAs) covering all the steps from topology choice, device sizing, compensation techniques, optimization of noise, power dissipation, bandwidth, large signal performance. As application cases, the amplifying blocks are adopted in designing analog filters.

Lectures are intended to deliver core concepts and methods, supported by notes and references to on-line material. Blended class sessions will present sample problems, guiding students to develop problem-solving strategies. Exercise classes will show students how to solve numerical problems thus strengthening their comprehension of the subjects. Labs are dedicated to design of CMOS amplifiers using CAD tools. The Lab activity provides realistic examples of the optimization procedures followed in real design practice. Design challenges are proposed during the course and active student participation is expected.

Introductory concepts and background: The transistor as an amplifier, performance figures: maximum voltage gain, fT, power amplification and Johnson’s limit. MOSFET: quadratic I-V dependence, channel length modulation. Transconductance and maximum gain. Subthreshold operation. Dependence on bias point of transconductance and cut-off frequency. Stray capacitance. Multifinger MOSFET’s. Technology platforms.

OTA's and OP-AMP's: The differential stage with resististive loads. Performance of current mirrors. Effects of current mirror on differential and common mode gains. CMOS OTA’s. Two stages topology. Bias and systematic offset. Device Matching. Pelgrom’s formula. Input voltage offset. Cascoded mirrors. Impact on gain and CMRR. Frequency response. Pole splitting and GBWP. Slew Rate. GBWP/SR ratio. Alternative compensation strategies with buffers and nulling resistor. Single stage OTA’s. Telescopic/folded cascode topologies. Feed-forward compensation and impact on in-band doublet. Class AB OTA's. OP-AMPs and output stages.  

Complements on Noise: variance and power spectrum. Noise sources. Physical models of thermal noise and shot noise. Noise sources in FET's, input equivalent noise sources. 1/f noise and Tvidis formula. Input equivalent noise sources of OP-AMP’s.

Active filters: Introduction to active filters. First order cells. Canonical form for the pole pair. Q- factor of the pair. Filter sensitivity. Second-order cells. The Sallen-Key cell, loop gain, sizing options, impact on filter sensitivity. The Universal filter (KHN cell). Tow-Thomas cell. Options for filter synthesis: cascade of active cells, resonant ladder networks. Active inductors. Quality factor and noise. Implementation of active inductors with amplifiers and transconductors. Synthesis with integrators. Switched capacitor filters. SC-integrator. Output spectrum of a switched capacitor stage. Stray insensitive switches. Non-inverting integrator. Non-idealities of SC filters: finite gain, clock feed-through.

No formal pre-requisite exists. However, students are required to know the basics of linear circuit analysis, MOSFET operation, small signal operation and frequency response of elementary transistor topologies, principles of feedback theory and methods to assess and tailor stability margin of feedback circuits.

Assessment is based on a final exam consisting of a written exam followed by an oral. The written exam is a 3-hours, closed-book test devoted to the quantitative solution of two problems. Students who pass the written exam go through the oral exam, consisting of a discussion of two topics randomly picked from a list made available on BeeP. Those who have submitted solutions to the design challenges will have up to additional points. At the oral, the student is asked to discuss the selected topics, clearly stating the framework, deriving the quantitative results and, then, summarizing their main implications. The oral exam results in an adjustment (-2/30 to +2/30) of the written exam result, thus leading to the final grade.