Course description and objectives
This course focuses on the design concepts and architectures underlying modern digital integrated circuits. The objective is to understand how to use individual devices to build combinational logic gates, sequential logic circuits , and complex architectures under constraints on reliability, performance, design time, area, and power consumption.
At the completion of this course, a student is expected to be able to: (i) analyze and design combinational and sequential digital circuits in different logic families; (ii) analyze the eﬀect of interconnect parasitics on circuit performance; (iii) design simple digital modules, such as finite state-machines, memories (SRAM, DRAM) and arithmetic circuits (adders, multipliers and digital comparators)
Introductory concepts and background: a historical perspective: from vacuum tube to transistor era, issues in digital integrated circuit design, quality metrics of a digital circuit (cost of an integrated circuit, functionality and reliability, static and dynamic performance, power and energy consumption).
The devices: the diode, the MOS(FET) transistor (static and dynamic behavior), velocity saturation, unified model, secondary effects, mismatch and process variations, technology scaling.
The wire: interconnect parameters (capacitance, resistance and inductance), electrical wire model (lumped and distributed RC models), Elmore theorem, transmission line, effects of scaling.
The CMOS inverter: the static CMOS Inverter, switching threshold, noise margins, propagation delay, dynamic power Consumption, static power consumption, power- and energy-delay product technology scaling and its impact on the digital circuit metrics.
Combinational logic gates: static CMOS design (fully-complementary CMOS logic, pseudo-NMOS logic, differential cascode voltage switched logic, pass-transistor logic), dynamic logic (basic principles, speed and power dissipation of dynamic Logic, cascading dynamic gates).
Sequential logic circuits: latches and flip-flops as basic sequential element, timing metrics for sequential circuits, static latches and flip-flops (multiplexer-based latches, master-slave Edge-Triggered flip-flop), SR flip-flop, JK flip-flop, toggle flip-flop, dynamic latches and flip-flop, C2MOS latches, True Single-Phase Clocked (TCSP) flip-flop, pulse flip-flop, pipelining as approach to optimize sequential circuits, finite state-machines (FSMs).
Arithmetic circuits: half-adder, full-adder, circuit implementation of single-bit adder, multi-bit adder (ripple carry, carry-skip, linear carry-select, root-square carry-select), multiplier (array and carry-save multiplier), digital comparators, 2’complement representatiojn of signed numbers, subtractors, digital comparators, equality circuits.
Semiconductor memories: memory classification, memory architectures and building blocks, read-only memories (ROM), nonvolatile read-write memories (RAM), static RAM, dynamic RAM, memory peripheral circuitry (address decoders, sense amplifiers, voltage references, drivers/buffers).