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| Academic Year |
2024/2025 |
| Name |
Dott. - MI (1380) Ingegneria dell'Informazione / Information Technology |
| Programme Year |
1 |
| ID Code |
062760 |
| Course Title |
ACCELERATING DATA PROCESSING IN THE POST-MOORE ERA |
| Course Type |
MONO-DISCIPLINARY COURSE |
| Credits (CFU / ECTS) |
5.0 |
| Course Description |
The combination of emerging data-intensive cloud applications, that exhibit complex patterns dominated by large transfers as well as distributed processing, with the end of Moore's law and Dennard scaling, requires a clean-slate approach on the design of modern high-performance computing (HPC) platforms. Here, a recent trend is to leverage new programmable devices (i.e., smart network interface cards, smart solid disk state controllers) to offload computation and save precious CPU cycles. In this scenario, NICs and SSDs are now no longer simple peripherals but complete compute platforms featuring memory resources and processing capabilities.
This course targets FPGA-implemented NICs, e.g., AMD Alveo cards, and focus on understanding how to maximize the performance of an HPC node through hardware-software co-designs. To achieve this, we consider three different aspects: (1) we discuss the architectures and design challenges of available NICs highlighting their pros and cons; (2) we explore the host-to-device interface by presenting the extended Berkley Packet Filter (eBPF), a technology that it is used to safely and efficiently extend the capabilities of the Linux kernel at runtime without requiring changes to kernel source code or loading kernel modules; (3) finally, we present a systematic hardware design and verification methodology to augment the NICs with ad-hoc accelerators and interconnects to perform the computational offload.
The course aims at creating a deep understanding of the data-centric design for HPC by combining operating system-level concepts with a hardware-level design and verification methodology used to develop advanced digital systems. This will be done by presenting a full-stack approach to packet processing in high-performance servers targeting NICs as the reference computational offload device.
The course capitalizes the background created in some of the courses at the bachelor degree related to computer architecture, operating systems and computer networks.
Detailed programme ? (topics and timeslots) -
1. Introduction and background (4h)
(a) Datacenter ecosystem;
(b) Quality metrics in the datacenters;
(c) Current challenges: scaling processing through accelerator-centric designs and communication protocols.
2. A methodology to design hardware offloads in datacenters (using SV) (8h)
(a) State diagrams and algorithmic state machines with datapath charts (ASMD);
(b) Regular sequential circuits, FSM (finite-state machines), and FSMD (finite-state machines with datapath);
(c) Functional verification of complex digital systems using SV.
3. A methodology to design software offloads in datacenters (using eBPF) (6h)
(a) Linux programming fundamentals;
(b) eBPF virtual machine, Linux verifier and trade-offs when inserting new functionalities at different hook points;
(c) An eBPF methodology for creating efficient software-based offloads targeting packet-processing operations.
4 Projects presentation, discussion, and kick-off (4h)
5. Applications and advanced system-level design tools (4h)
(a) Exploring Open-hardware RISC-V-based System-on-Chip;
(b) Exporing the OpenNIC project for SmartNICs;
(c) Analysing the link between eBPF and OpeNIC for advanced user-space processing. |
| Scientific-Disciplinary Sector (SSD)
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Alphabetical group
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Name
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Teaching Assignment Details
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From (included)
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To (excluded)
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A
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ZZZZ
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Antichi Gianni, Miano Sebastiano, Zoni Davide
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