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Dati Insegnamento
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Manifesto
Dati Insegnamento
Contesto
Anno Accademico 2023/2024
Corso di Studi Dott. - MI (1380) Ingegneria dell'Informazione / Information Technology
Anno di Corso 1

Scheda Insegnamento
Codice Identificativo 061638
Denominazione Insegnamento HARDWARE DESIGN AND VERIFICATION OF DIGITAL COMPUTING PLATFORMS
Tipo Insegnamento MONODISCIPLINARE
Crediti Formativi Universitari (CFU) 5.0
Programma sintetico The course aims at creating a bridge toward the popular design approaches and the use of complex and reliable functional verification processes, as required during the development of advanced hardware digital systems. The topic will be addressed by presenting a unified approach covering design and verification methodologies and the related hardware description and verification language (HDVL) for the implementation and functional verification of complex synchronous digital hardware systems. The course targets two main classes of students. Students with architectural background in computing platforms will understand how to implement state-of-the-art (scalar and super-scalar CPUs) as well as novel computing architectures (custom hardware accelerators) targeting synchronous digital systems. Students with microarchitectural background will understand how to design, optimize and verify digital hardware systems to optimize PPA (Power Performance Area) by leveraging commercial (e.g., Cadence and Xilinx) and academic (e.g. Verilator, Icarus Verilog, and Yosys) hardware toolchains. The course is intended to complement the skills of the student towards the systematic design, implementation, and functional verification of synchronous digital systems. The course capitalizes the background created in some of the courses of the bachelor (e.g., ACSO, ACA, Reti Logiche) also providing a solid link with advanced courses in the extended computer architecture research area, e.g., the design and optimization of compilers' backend, the design of custom AI and HPC accelerators, hardware security, and edge computing.
Settori Scientifico Disciplinari (SSD) --

Dettaglio
Scaglione Nome Programma dettagliato
Da (compreso) A (escluso)
A ZZZZ Zoni Davide
manifestidott v. 1.10.0 / 1.10.0
Area Servizi ICT
22/06/2024